1. Field of the Invention
The present invention relates to a CCD solid state imaging device with a lateral overflow drain structure and a driving method thereof, and more particularly to a device and method which reduce power consumption.
2. Description of Related Art
In a solid state imaging device, when excess information charges are generated in an imaging section, a phenomenon known as “blooming” in which information charges overflow into an adjacent pixel often occurs. In one anti-blooming technique, an overflow drain structure is provided for discharging unnecessary information charges. The overflow drain structures include the vertical overflow drain and the lateral overflow drain.
Such a lateral overflow drain is used in frame transfer CCD solid state imaging devices. FIG. 5 schematically shows a configuration of a frame transfer CCD solid state imaging device. Referring to FIG. 5, a frame transfer CCD solid state imaging device 2 comprises an imaging section 2i, a storage section 2s, a horizontal transfer section 2h, and an output section 2d. A two-dimensional array of information charges generated in the imaging section 2i is transferred at a high rate to the storage section 2s. The information charges, which are stored in the storage section 2s, are also transferred to the horizontal transfer section 2h for every one row. Then, the information charges are further transferred from the horizontal transfer section 2h to the output section 2d pixel by pixel. The output section 2d converts a charge amount for each pixel into a voltage as a CCD output.
Each of the imaging section 2i and the storage section 2s comprises a plurality of vertical shift registers composed of a plurality of channel regions extending in the vertical direction in parallel to each other and a plurality of transfer electrodes extending in the horizontal direction in parallel to each other.
In the case of a CCD solid state imaging device employing a lateral overflow drain structure, a drain region is formed between adjacent vertical shift registers.
FIG. 6 is a schematic plan view showing a part of the imaging section 2i or the storage section 2s of a frame transfer CCD solid state imaging device employing a conventional lateral overflow drain structure. In the approximately center position between adjacent channel regions 4 of a vertical shift register, a drain region 8 is formed, and a separation region 10 is formed between the drain region 8 and the channel region 4. The drain region 8 is disposed parallel to the channel region 4 and is formed by doping high density N-type dopant ions to have a predetermined width. The separation region 10 is formed by doping P-type dopant ions between the channel region 4 and the drain region 8. The separation region 10 creates a potential barrier between the channel region 4 and the drain region 8.
A transfer electrode 12 is formed on a semiconductor substrate via an oxide film so as to extend in the direction intersecting the channel region 4. A plurality of transfer electrodes 12 are disposed parallel to each other and are electrically insulated from each other. Each transfer electrode 12 receives a vertical transfer clock φf. By applying a vertical transfer clock φf to the transfer electrode 12, the state of the potential well formed in the channel region 4 is controlled for sequentially transferring the accumulated information charge.
In the case of three-phase driving, for example, clock pulses φ1, φ2, and φ3 are applied to the transfer electrodes 12-1, 12-2, and 12-3, respectively. Namely, in the three-phase driving, three transfer electrodes 12-1 to 12-3 are designated as one pixel, and one light receiving pixel or an information charge is defined for each set of three transfer electrodes 12-1 to 12-3.
At the time of imaging, a clock pulse φ2, for example, is caused to rise to H level, and a potential well is formed beneath the transfer electrode 12-2 of the imaging section 2i. The information charges generated by incident light entering the semiconductor substrate moves to the neighboring potential well and is accumulated in the potential well.
Further, due to clock pulses φ1 to φ3 having different phases, the potential well formed beneath the transfer electrode 12 can be moved in a predetermined direction. Thus, the information charges stored in the potential well is transferred (in the downward direction in FIG. 6, for example) using the channel region 4 as a transfer path.
FIG. 7A is a schematic cross sectional view taken along line X-X of FIG. 6, and FIG. 7B shows the potential state at a portion corresponding to the cross section of FIG. 7A. Referring to FIG. 7A, an N well 20, an N+ diffusion layer 22, and P− diffusion layer 24, respectively corresponding to the channel region 4, the drain region 8, and the separation region 10, are formed on a surface of a p type semiconductor substrate Psub. On the substrate surface, the transfer electrode 12 is disposed via a gate oxide film 26. In FIG. 7B, the vertical axis indicates potential, with the positive potential increasing in the downward direction. The N well 20 may be placed in a depletion state by a voltage to the transfer electrode 12 to thereby create a potential well 30. The information charges 32 can be accumulated in the potential well 30. The N+ diffusion layer 22 creates a positive potential drain 34, and the P− diffusion layer, which corresponds to the separation region 10, forms a potential barrier 36 between the potential well 30 of the transfer channel and the drain 34.
A discharge clock φb is applied to the drain region 8. The discharge clock is held to L level (5V, for example) at normal times. In such a state, the potential barrier 36 is created between the channel region 4 and the drain region 8. When a CCD solid state imaging device is exposed to very high intensity light and a large amount of information charges are generated in the channel region, for example, charges exceeding the storage capacity of the channel region spill over the potential barrier 36 into the drain region 8 and are discharged. As a result, blooming, in which excess charges spills over into adjacent pixels and cause image disturbance, can be prevented.
The above structure can also be used to operate an electronic shutter. In this operation, a discharge clock φb to be applied to the drain region 8 rises to H level, while a vertical transfer clock φf applied to the transfer electrode 12 falls to L level. Consequently, the depth of the potential well in the channel region 4 shallows and the barrier between the channel region 4 and the drain region 8 is lowered (see a dotted line 36 in FIG. 7(b)). This causes the information charges to move along the slope of the potential, so that the information charges accumulated in the channel region 4 are collectively discharged into the drain region 8 via the separation region 10. With this operation, all the information charges stored in the imaging section 2i and the storage section 2s are discharged and at this point in time, a new exposure period starts in the imaging section 2i. 